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| 1 features ? high-performance, low-power avr ? 8-bit microcontroller ? advanced risc architecture ? 90 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? non-volatile progra m and data memories ? 1k byte in-system programm able flash program memory endurance: 1,000 write/erase cycles ? 64 bytes eeprom endurance: 100,000 write/erase cycles ? programming lock for flash program data security ? peripheral features ? interrupt and wake-up on pin change ? two 8-bit timer/counters with separate prescalers ? one 150 khz, 8-bit high-speed pwm output ? 4-channel 10-bit adc one differential voltage input with optional gain of 20x ? on-chip analog comparator ? programmable watchdog timer with on-chip oscillator ? special microcontroller features ? in-system programmable via spi port ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal, calibrated 1.6 mhz tunable oscillator ? internal 25.6 mhz clock generator for timer/counter ? external and internal interrupt sources ? low-power idle and power-down modes ? power consumption at 1.6 mhz, 3v, 25 c ? active: 3.0 ma ? idle mode: 1.0 ma ? power-down: < 1 a ? i/o and packages ? 8-lead pdip and 8-lead soic: 6 programmable i/o lines ? operating voltages ? 2.7v - 5.5v ? internal 1.6 mhz system clock pin configuration 1 2 3 4 8 7 6 5 ( reset/adc0) pb5 (adc3) pb4 (adc2) pb3 gnd vcc pb2 (adc1/sck/t0/int 0) pb1 (ain1/miso/oc1a) pb0 (ain0/aref/mosi) pdip/soic 8-bit microcontroller with 1k byte flash attiny15l not recommended for new design rev. 1187h?avr?09/07
2 attiny15l 1187h?avr?09/07 description the attiny15l is a low-power cmos 8-bit microcontroller based on the avr risc architecture. by executing powerful instructions in a single clock cycle, the attiny15l achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the attiny15l provides 1k by te of flash, 64 bytes eepr om, six genera l purpose i/o lines, 32 general purpose working register s, two 8-bit timer/counters, one with high- speed pwm output, internal osc illators, internal and external interrupts, programmable watchdog timer, 4-channel 10-bit analog-to-digital converter with one differential volt- age input with optional 20x gain, and three software-selectable power-saving modes. the idle mode stops the cpu while a llowing the adc, an alog comparator, timer/counters and interrupt system to continue functioning. the adc noise reduction mode facilitates high-accuracy adc measurem ents by stopping the cpu while allowing the adc to continue functioning. the power-down mode saves the register contents but freezes the osc illators, disabling all other chip functions until the next interrupt or hard- ware reset. the wake-up or interrupt on pin change features enable the attiny15l to be highly responsive to external events, st ill featuring the lowest power consumption while in the power-saving modes. the device is manufactured using atmel?s hi gh-density, non-volatile memory technol- ogy. by combining a risc 8-bit cpu with flash on a monolithic chip, the attiny15l is a powerful microcontroller that provides a highly flexible and cost-efficient solution to many embedded control applications. the peripheral features make the attiny15l par- ticularly suited for battery chargers, lighting ballasts and all kinds of intelligent sensor applications. the attiny15l avr is supported with a full suite of program and system development tools including macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits. 3 attiny15l 1187h?avr?09/07 block diagram figure 1. the attiny15l block diagram program counter internal oscilla tor watchdog timer stack pointer program flash hardware stack mcu control register general purpose registers instruction register timer/ counter0 instruction decoder data dir. reg.port b data register port b programming logic timing and control timer/ counter1 mcu status register status register alu port b drivers pb0-pb5 vcc gnd control lines + - analog comparator 8-bit data bus z isp module interrupt unit data eeprom internal oscilla tor tunable analog mux adc 4 attiny15l 1187h?avr?09/07 pin descriptions vcc supply voltage pin. gnd ground pin. port b (pb5..pb0) port b is a 6-bit i/o port. pb4..0 are i/o pins that can provide internal pull-ups (selected for each bit). pb5 is input or open-drain output. the use of pin pb5 is defined by a fuse and the special function associated with this pin is external reset. the port pins are tri- stated when a reset condition becomes active, even if the clock is not running. port b also accommodates analog i/o pins. t he port b pins with alternate functions are shown in table 1. analog pins up to four analog inputs can be selected as inputs to analog-to-digital converter (adc). internal oscillators the internal oscillator provides a clock rate of nominally 1.6 mhz for the system clock (ck). due to large initial variation (0.8 -1.6 mhz) of the internal oscillator, a tuning capa- bility is built in. through an 8-bit control register ? osccal ? the system clock rate can be tuned with less than 1% steps of the nominal clock. there is an internal pll that provides a 16x clock rate locked to the system clock (ck) for the use of the peripheral timer/counter1. the nominal frequency of this peripheral clock, pck, is 25.6 mhz. table 1. port b alternate functions port pin alternate function pb0 mosi (data input line for memory downloading) aref (adc voltage reference) ain0 (analog comparator positive input) pb1 miso (data output line for memory downloading) oc1a (timer/counter pwm output) ain1 (analog comparator negative input) pb2 sck (serial clock input for serial programming) int0 (external interrupt0 input) adc1 (adc input channel 1) t0 (timer/counter0 external counter input) pb3 adc2 (adc input channel 2) pb4 adc3 (adc input channel 3) pb5 reset (external reset pin) adc0 (adc input channel 0) 5 attiny15l 1187h?avr?09/07 attiny15l architectural overview the fast-access register file concept contains 32 x 8-bit general purpose working reg- isters with a single-clock-cycle access time. this means that during one single clock cycle, one alu (arithmetic logic unit) operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. two of the 32 registers can be used as a 16-bit pointer for indirect memory access. this pointer is called the z-pointer, and can address the register file, io file and the flash program memory. figure 2. the attiny15l avr risc architecture the alu supports arithmetic and logic functions between registers or between a con- stant and a register. single-register operations are also executed in the alu. figure 2 shows the attiny15l avr risc microcontroller architecture. the avr uses a harvard architecture concept with separate memories and buses for program and data memo- ries. the program memory is accessed with a two-stage pipeline. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system programmable flash memory. with the relative jump and relative call in structions, the whole address space is directly accessed. all avr instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is a 3-level-deep hardware stack dedicated for subrou- tines and interrupts. the i/o memory space contains 64 addresse s for cpu peripheral functions as control registers, timer/counters and other i/o functions. the memory spaces in the avr architecture are all linear and regular memory maps. 512 x 16 program flash instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu direct addressing status and test control registrers interrupt unit 2 x 8-bit timer/counter watchdog timer analog comparator i/o lines data bus 8-bit spi unit adc 64 x 8 eeprom 6 attiny15l 1187h?avr?09/07 a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all the different interrupts have a sep- arate interrupt vector in the interrupt vector table at the beginning of the program memory. the different interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the general purpose register file figure 3 shows the structure of the 32 general purpose registers in the cpu. figure 3. avr cpu general purpose working registers all the register operating instructions in t he instruction set have direct- and single-cycle access to all registers. the only exception is the five constant arithmetic and logic instructions sbci, subi, cpi, andi, and ori between a constant and a register and the ldi instruction for load-immediate constant data. these instructions apply to the second half of the registers in the register file ? r16..r31. the general sbc, sub, cp, and, or, and all other operations between two registers or on a single-register apply to the entire register file. registers 30 and 31 form a 16-bit pointer (the z-pointer) which is used for indirect flash memory and register file access. when the r egister file is accessed, the contents of r31 is discarded by the cpu. the alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all the 32 general purpose working registers. within a single clock cycle, alu operations between regis- ters in the register file are executed. the alu operations are divided into three main categories ? arithmetic, logic and bit-functions. some microcontrollers in the avr prod- uct family feature a hardware multiplier in the arithmetic part of the alu. the flash program memory the attiny15l contains 1k byte on-chip, in-system programmable flash memory for program storage. since all instructions are si ngle 16-bit words, the flash is organized as 512 x 16 words. the flash memory has an endurance of at least 1,000 write/erase cycles. the attiny15l program counter is nine bits wide, thus addressing the 512 words flash program memory. see page 54 for a detailed description on flash memory programming. 70 r0 r1 r2 general ? purpose ? working r28 registers r29 r30 (z-register low byte) r3 r31 (z-register high byte) 7 attiny15l 1187h?avr?09/07 the program and data addressing modes the attiny15l avr risc microcontroller supports powerful and efficient addressing modes. this section describes the vari ous addressing mode s supported in the attiny15l. in the figures, op means the operation code part of the instruction word. to simplify, not all figures show the exact location of the addressing bits. register direct, single- register rd figure 4. direct single-register addressing the operand is contained in register d (rd). register indirect figure 5. indirect register addressing the register accessed is the one pointed to by the z-register low byte (r30). register direct, two registers rd and rr figure 6. direct register addressing, two registers register file 0 31 3 0 z-register 8 attiny15l 1187h?avr?09/07 operands are contained in register r (rr) and d (rd). the result is stored in register d (rd). i/o direct figure 7. i/o direct addressing operand address is contained in 6 bits of the instruction word. ?n? is the destination or source register address. relative program addressing, rjmp and rcall figure 8. relative program memory addressing program execution continues at address pc + k + 1. the relative address k is -2048 to 2047. constant addressing using the lpm instruction figure 9. code memory constant addressing +1 $1ff 9 attiny15l 1187h?avr?09/07 constant byte address is specified by the z-register contents. the 15 msbs select word address (0 - 511), and lsb selects low byte if cleared (lsb = 0) or high byte if set (lsb = 1). subroutine and interrupt hardware stack the attiny15l uses a 3-level-deep hardware stack for subroutines and interrupts. the hardware stack is nine bits wide and stores the program counter (pc) return address while subroutines and interrupts are executed. rcall instructions and interrupts push the pc return address onto stack level 0, and the data in the other stack levels 1 - 2 are pushed one level deeper in the stack. when a ret or reti instruction is executed the returning pc is fetched from stack level 0, and the data in the other stack levels 1 - 2 are popped one level in the stack. if more than three subsequent subroutine calls or interrupts are executed, the first val- ues written to the stack are overwritten. pushing four return addresses a1, a2, a3, and a4 followed by four subroutine or interrupt returns, will pop a4, a3, a2, and once more a2 from the hardware stack. the eeprom data memory the attiny15l contains 64 bytes of data ee prom memory. it is organized as a sepa- rate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described on page 36, spec ifying the eeprom address register, the eeprom data register, and th e eeprom control register. memory access and instruction execution timing this section describes the general access timing concepts for instruction execution and internal memory access. the avr cpu is driven by the system cloc k ?, directly generated from the external clock crystal for the chip. no in ternal clock division is used. figure 10 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 10. the parallel instruction fetches and instruction executions figure 11 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. system clock ? 1st instruction fetch 1st instruction execute 2nd instruction fetch 2 nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 10 attiny15l 1187h?avr?09/07 figure 11. single cycle alu operation i/o memory the i/o space definition of the attiny15l is shown in table 2. system clock ? total execution time r egister operands fetch alu operation execute result write back t1 t2 t3 t4 table 2. attiny15l i/o space (1) address hex name function $3f sreg status register $3b gimsk general interrupt mask register $3a gifr general interrupt flag register $39 timsk timer/counter interrupt mask register $38 tifr timer/counter interrupt flag register $35 mcucr mcu control register $34 mcusr mcu status register $33 tccr0 timer/counter0 control register $32 tcnt0 timer/counter0 (8-bit) $31 osccal oscillator calibration register $30 tccr1 timer/counter1 control register $2f tcnt1 timer/counter1 (8-bit) $2e ocr1a timer/counter1 output compare register a $2d ocr1b timer/counter1 output compare register b $2c sfior special function i/o register $21 wdtcr watchdog timer control register $1e eear eeprom address register $1d eedr eeprom data register $1c eecr eeprom control register $18 portb data register, port b $17 ddrb data direction register, port b $16 pinb input pins, port b $08 acsr analog comparator c ontrol and status register $07 admux adc multiplexer select register 11 attiny15l 1187h?avr?09/07 note: 1. reserved and unused locations are not shown in the table. all attiny15l i/o and peripheral registers are placed in the i/o space. the i/o locations are accessed by the in and out instructions transferring data between the 32 general purpose working registers and the i/o space. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these regis- ters, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set chapter for more details. for compatibility with future devices, reserved bits should be written zero if accessed. reserved i/o memory addresses should never be written. the i/o and peripheral control registers are explained in the following sections. the status register ? sreg the avr status register ? sreg ? at i/o space location $3f is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individual interrupt enable control is then performed in the interrupt mask registers ? gimsk and timsk. if the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the gimsk and timsk values. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source and destination for the operated bit. a bit from a register in the register file can be cop- ied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half-carry flag the half-carry flag h indicates a half-carry in some arithmetic operations. see the instruction set description for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s comple- ment overflow flag v. see the instruction set description for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the instruction set description for detailed information. $06 adcsr adc control and status register $05 adch adc data register high $04 adcl adc data register low table 2. attiny15l i/o space (1) (continued) address hex name function bit 76543210 $3f i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 12 attiny15l 1187h?avr?09/07 ? bit 2 ? n: negative flag the negative flag n indicates a negative result after the different arithmetic and logic operations. see the instruction set description for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result after the different arithmetic and logic opera- tions. see the instruction set description for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the instruction set description for detailed information. reset and interrupt handling the attiny15l provides eight interrupt s ources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all the interrupts are assigned individual enable bits that must be set (one) together with the i-bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 3. the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 (the external interrupt request 0), etc. table 3. reset and interrupt vectors vector no. program address source interrupt definition 1 $000 reset external reset, power-on reset, brown-out reset, and watchdog reset 2 $001 int0 external interrupt request 0 3 $002 i/o pins pin change interrupt 4 $003 timer1, compa timer/counter1 compare match a 5 $004 timer1, ovf timer/counter1 overflow 6 $005 timer0, ovf timer/counter0 overflow 7 $006 ee_rdy eeprom ready 8 $007 ana_comp analog comparator 9 $008 adc adc conversion complete 13 attiny15l 1187h?avr?09/07 the most typical and general program setup for the reset and interrupt vector addresses are: address labels code comments $000 rjmp reset ; reset handler $001 rjmp ext_int0 ; irq0 handler $002 rjmp pin_change ; pin change handler $003 rjmp tim1_cmp ; timer1 compare match $004 rjmp tim1_ovf ; timer1 overflow handler $005 rjmp tim0_ovf ; timer0 overflow handler $006 rjmp ee_rdy ; eeprom ready handler $007 rjmp ana_comp ; analog comparator handler $008 rjmp adc ; adc conversion handler ; $009 main: 14 attiny15l 1187h?avr?09/07 figure 12. reset logic note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling). table 4. reset characteristics (v cc = 5.0v) (1) symbol parameter condition min typ max units v pot power-on reset threshold voltage (rising) bod disabled 1.0 1.4 1.8 v bod enabled 1.7 2.2 2.7 v power-on reset threshold voltage (falling) (1) bod disabled 0.4 0.6 0.8 v bod enabled 1.7 2.2 2.7 v v rst reset pin threshold voltage ? ? 0.85 v cc v v bot brown-out reset threshold voltage (bodlevel = 1) 2.3 2.7 2.9 v (bodlevel = 0) 3.4 4.0 4.3 v mcu status register (mcusr) brown-out reset circuit boden bodlevel delay counters cksel[1:0] ck timeout wdrf borf extrf porf data b u s tunable internal oscillator watchdog oscillator watchdog timer reset circuit power-on reset circuit 15 attiny15l 1187h?avr?09/07 notes: 1. on power-up, the start-up time is increased with typical 0.6 ms. 2. ?0? means programmed, ?1? means unprogrammed. table 5 shows the start-up times from reset. when the cpu wakes up from power- down, only the clock-counting part of the star t-up time is used. t he watchdog oscillator is used for timing the real-time part of th e start-up time. the numb er watchdog oscilla- tor cycles used for each time-out is shown in table 6. the frequency of the watchdog oscillator is voltage dependent as shown in the electri- cal characteristics section on page 64. the device is shipped with cksel = ?00?. power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detec- tion level is nominally defined in tabl e 4. the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes a delay counter, which deter- mines the delay, for which the de vice is kept in reset after v cc rise. the time-out period of the delay counter can be defined by the user through the cksel fuses. the different selections for the delay period are presented in table 5. the reset signal is activated again, without any delay, when the v cc decreases below detection level. table 5. reset delay selections (1) boden (2) cksel [1:0] (2) start-up time, t tout at v cc = 2.7v start-up time, t tout at v cc = 5.0v recommended usage x 00 256 ms + 18 ck 64 ms + 18 ck bod disabled, slowly rising power x 01 256 ms + 18 ck 64 ms + 18 ck bod disabled, slowly rising power x 10 16 ms + 18 ck 4 ms + 18 ck bod disabled, quickly rising power 1 11 18 ck + 32 s 18 ck + 8 s bod disabled 0 11 18 ck + 128 s 18 ck + 32 s bod enabled table 6. number of watchdog oscillator cycles v cc conditions time-out number of cycles 2.7v 32 s 8 2.7v 128 s 32 2.7v 16 ms 4k 2.7v 256 ms 64k 5.0v 8 s 8 5.0v 32 s 32 5.0v 4 ms 4k 5.0v 64 ms 64k 16 attiny15l 1187h?avr?09/07 figure 13. ?mcu start-up, reset tied to v cc figure 14. mcu start-up, reset extended externally external reset an external reset is generated by a lo w-level on the reset pin. reset pulses longer than 500 ns will gener ate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage (v rst ) on its positive edge, the delay timer starts the mcu after the time-out period t tout has expired. figure 15. external reset during operation vcc reset t ime-out i nternal reset t tout v pot v rst vcc reset t ime-out i nternal reset t tout v pot v rst 17 attiny15l 1187h?avr?09/07 brown-out detection attiny15l has an on-chip brown-out detect ion (bod) circuit for monitoring the v cc level during the operation. the bod circuit can be enabled/disabled by the fuse boden. when boden is enabled (boden programmed), and v cc decreases below the trigger level, the brown-out reset is immediately activated. when v cc increases above the trigger level, the brown-out rese t is deactivated after a delay. the delay is defined by the user in the same way as the delay of por signal, in table 5. the trigger level for the bod can be selected by the fuse bodlevel to be 2.7v (bodlevel unprogrammed), or 4.0v (bodlevel programmed). the trigger level has a hysteresis of 50 mv to ensure spike-free brown-out detection. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than 3 s for trigger level 4.0v, 7 s for trigger level 2.7v (typical values). figure 16. brown-out reset during operation (1) note: 1. the hysteresis on v bot : v bot+ = v bot + 25 mv, v bot- = v bot - 25 mv. watchdog reset when the watchdog times out, it will generate a short rese t pulse of one ck cycle dura- tion. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 34 for details on operation of the watchdog timer. figure 17. watchdog reset during operation v cc reset t ime-out i nternal reset v bot- v bot+ t tout 1 ck cycle 18 attiny15l 1187h?avr?09/07 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 7..4 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. ? bit 3 ? wdrf: watchdog reset flag this bit is set (one) if a watchdog reset occurs. the bit is reset (zero) by a power-on reset, or by writing a logical ?0? to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set (one) if a brown-out reset occurs. the bit is reset (zero) by a power-on reset, or by writing a logical ?0? to the flag. ? bit 1 ? extrf: external reset flag this bit is set (one) if a external reset occurs. the bit is reset (zero) by a power-on reset, or by writing a logical ?0? to the flag. ? bit 0 ? porf: power-on reset flag this bit is set (one) if a powe r-on reset occurs. the bit is reset (zero) by writing a logical ?0? to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. internal voltage reference attiny15l features an internal bandgap reference with a nominal voltage of 1.22v. this reference is used for brown-out detection, and it can be used as an input to the analog comparator. the 2.56v reference to the adc is generated from the internal bandgap reference. voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the maximum start-up time is 10 s. to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by programming the boden fuse). 2. when the bandgap reference is connected to the analog comparator (by setting the ainbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the ainbg bit, the user must always allow the reference to start-up before the output from the analog comparator is used. the bandgap reference uses typically 10 a, and to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the ref- erence is turned off before entering power-down mode. bit 76543210 $34 ????wdrfborfextrfporfmcusr read/writerrrrr/wr/wr/wr/w initial value0000 see bit description 19 attiny15l 1187h?avr?09/07 interrupt handling the attiny15l has two 8-bit interrupt mask control registers: gimsk (general inter- rupt mask register) and timsk (timer/counter interrupt mask register). when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all inter- rupts are disabled. the user software can set the i-bit (one) to enable interrupts. the i- bit is set (one) when a return from interrupt instruction (reti) is executed. when the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. some of the interrupt flags can also be cleared by writing a logical ?1? to the flag bit position(s) to be cleared. if an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the in terrupt is enab led, or the flag is cleared by software. if one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding inte rrupt flag(s) will be set and remembered un til the global interrupt enable bit is se t (one), and will be execut ed by order of priority. note that external level in terrupt does not hav e a flag, and will only be remembered for as long as the interrupt condition is present. note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. this must be handled by software. interrupt response time the interrupt execution response for all the enabled avr interrupts is four clock cycles minimum. after the four clock cycles the program vector address for the actual interrupt handling routine is executed. during this 4-clock-cycle period, the program counter (nine bits) is pushed onto the stack. the vector is often a relative jump to the interrupt routine, and this jump takes two clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed bef ore the interrupt is served . if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. a return from an interrupt handling routine ta kes four clock cycles. during these four clock cycles, the program c ounter (nine bits) is popped back from the stack. when avr exits from an interrupt, it will always return to the main program and execute one more instruction be fore any pending interrupt is served. the general interrupt mask register ? gimsk ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. ? bit 6 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is activated. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control regist er (mcucr) define whether the external interrupt is activated on rising or falling edge, on pi n change, or low level of the int0 pin. activity on the pin will cause an interrupt request even if int0 is configured as an output. bit 76543210 $3b ? int0 pcie ? ? ? ? ? gimsk read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 20 attiny15l 1187h?avr?09/07 the corresponding interrupt of external inte rrupt request 0 is executed from program memory address $001. see also ?external interrupts.? ? bit 5 ? pcie: pin change interrupt enable when the pcie bit is set (one) and the i-bit in the status register (sreg) is set (one), the interrupt on pin change is enabled. any change on an y input or i/o pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from program memory address $002. see also ?pin change interrupt.? ? bits 4..0 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. the general interrupt flag register ? gifr ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. ? bit 6 ? intf0: external interrupt flag0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (one), the mcu will jump to the interrupt vector at add ress $001. the flag is cleared when the interrupt routine is executed. alternatively, th e flag can be cleared by writing a logical ?1? to it. the flag is always cleared when int0 is conf igured as le vel interrupt. ? bit 5 ? pcif: pin change interrupt flag when an event on any input or i/o pin trigger s an interrupt request, pcif becomes set (one). if the i-bit in sreg an d the pcie bit in gimsk are set (one), the mcu will jump to the interrupt vector at address $002. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical ?1? to it. ? bits 4..0 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. the timer/counter interrupt mask register ? timsk ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. ? bit 6 ? ocie1a: timer/counter1 output compare interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare match, interrupt is enabled. the corresponding interrupt (at bit 76543210 $3a ?intf0pcif?????gifr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $39 ? ocie1a ? ? ? toie1 toie0 ? timsk read/write r r/w r r r r/w r/w r initial value 0 0 0 0 0 0 0 0 21 attiny15l 1187h?avr?09/07 vector $003) is executed if a compare match a in timer/counter1 occurs, i.e., when the ocf1a bit is set (one) in the timer/counter interrupt flag register (tifr). ? bit 5..3 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. ? bit 2 ? toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $004) is executed if an overflow in timer/counter1 occurs, i.e., when the tov1 bit is set (one) in the timer/counter interrupt flag register (tifr). ? bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $005) is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set (one) in the timer/counter interrupt flag register (tifr). ? bit 0 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. the timer/counter interrupt flag register ? tifr ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. ? bit 6 ? ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1a (output compare r egister 1a). ocf1a is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, ocf1a is cleared by writing a logical ?1? to the flag. when the i-bit in sreg, ocie1a, and ocf1a are set (one), the timer/counter1 compare match a interrupt is executed. ? bits 5..3 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. ? bit 2 ? tov1: timer/counter1 overflow flag the bit tov1 is set (one) when an overflow occurs in timer/counter1. tov1 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov1 is cleared by writing a logical ?1? to the flag. when the sreg i-bit, toie1 (timer/counter1 overflow interrupt enable) and tov1 are set (one), the timer/counter1 overflow interrupt is executed. bit 76543210 $38 ?ocf1a???tov1tov0?tifr read/write r r/w r r r r/w r/w r initial value 0 0 0 0 0 0 0 0 22 attiny15l 1187h?avr?09/07 ? bit 1 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logical ?1? to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable) and tov0 are set (one), the timer/counter0 overflow interrupt is executed. ? bit 0 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. external interrupt the external interrupt is triggered by the int0 pin. observe that, if enabled, the interrupt will trigger even if the in t0 pin is configured as an output. this f eature provides a way of generating a software interrupt. the external interrupt can be triggered by a falling or rising edge, a pin change, or a low level. this is set up as indicated in the specification for the mcu control register (mcucr). when the external interrupt is enabled and is configured as level-triggered, the interrupt will trigger as long as the pin is held low. the external interrupt is set up as described in the specification for the mcu control register (mcucr). pin change interrupt the pin change interrupt is triggered by any change in logical value on any input or i/o pin. change on pins pb4..0 will always ca use an interrupt. change on pin pb5 will cause an interrupt if the pin is configured as input or i/o, as described in the section ?pin descriptions? on page 4. obse rve that, if enabled, the inte rrupt will trigger even if the changing pin is configured as an output. this feature provides a way of generating a software interrupt. also observe that the pin change interrupt will trigger even if the pin activity triggers another interrupt, for example the external interrupt. this implies that one external event might cause several interr upts. the values on the pins are sampled before detecting edges. if pin change interrupt is enabled, pulses that last longer than one cpu clock period will gener ate an interrupt. shorter pulses are not guaranteed to generate an interrupt. the mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. ? bits 7 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. ? bit 6- pud: pull-up disable this pud bit must be set (one) to disable internal pull-up registers at port b. ? bit 5 ? se: sleep enable the se bit must be set (one) to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the pro- grammer?s purpose, it is recommended to set the sleep enable se bit just before the execution of the sleep instruction. bit 76543210 $35 ? pud se sm1 sm0 ? isc01 isc00 mcucr read/write r r/w r/w r/w r/w r r/w r/w initial value00000000 23 attiny15l 1187h?avr?09/07 ? bits 4, 3 ? sm1, sm0: sleep mode select bits 1 and 0 these bits select between the three avai lable sleep modes, as shown in table 7. for details, refer to ?sleep modes? below. ? bit 2 ? res: reserved bit this bit is a reserved bit in the attiny15l and always reads as zero. ? bits 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corresponding interrupt mask is set (one). the activity on the external int0 pin that acti- vates the interrupt is defined in table 8: note: 1. when changing the isc10/isc00 bits, int0 must be disabled by clearing its interrupt enable bit in the gimsk register. otherwise an interrupt can occur when the bits are changed. sleep modes to enter any of the three sleep modes, the se bit in mcucr must be set (one) and a sleep instruction must be executed. the sm1 and sm0 bits in the mcucr register select which sleep mode (idle, adc noise reduction or power-down) will be activated by the sleep instruction (see table 7). if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles, executes the interrupt routine and resumes execution from the instruction following sleep. on wake-up from power-down mode on pin change, two instruction cycles are executed before the pin change interrupt flag is updated. the contents of the register file, sram, and i/o memory are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. idle mode when the sm1/sm0 bits are ?00?, the sleep instruction forces the mcu into the idle mode, stopping the cpu but allowing the adc, analog comparator, timer/counters, watchdog and the interrupt system to continue operating. this enables the mcu to wake-up from external triggered interrupts as well as internal ones like the timer over- flow interrupt and watchdog reset. if the adc is enabled, a conversion starts automatically when this mode is entered. if wake-up from the analog comparator inter- rupt is not required, the analog comparator can be powered down by setting the adc- bit in the analog comparator control and status register (acsr). this will reduce power consumption in idle mode. table 7. sleep modes sm1 sm0 sleep mode 0 0 idle mode 0 1 adc noise reduction mode 1 0 power-down mode 11reserved table 8. interrupt 0 sense control (1) isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any change on int0 generates an interrupt request 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 24 attiny15l 1187h?avr?09/07 adc noise reduction mode when the sm1/sm0 bits are ?01?, the sleep instruction forces the mcu into the adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupt pin, pin change interrupt and the watchdog (if enabled) to continue operating. please note that the clock system including the pll is also active in the adc noise reduction mode. this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conv ersion starts automatically when this mode is entered. in addition to watchdog time-out and external reset, only an external level- triggered interrupt, a pin change interrupt or an adc interrupt can wake up the mcu. power-down mode when the sm1/sm0 bits are ?1 0?, the sleep instruction forc es the mcu into the power- down mode. only an external reset, a watc hdog reset (if enabled), an external level- triggered interrupt, or a pin change interrupt can wake up the mcu. note that if a level-triggered or pin change interrupt is used for wake-up from power- down mode, the changed level must be held for some time to wake up the mcu. this makes the mcu less sensitive to noise. th e changed level is sampled twice by the watchdog oscillator clock, and if the input has the required level during this time, the mcu will wake up. the period of the watchdog oscillator is 2.9 s (nominal) at 3.0v and 25 c. the frequency of the watc hdog oscillator is voltage- dependent as shown in the ?electrical characteristics? section. when waking up from the power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period. tuneable internal rc oscillator the internal rc oscillator provides a fixed 1.6 mhz clock (nominal at 5v and 25 c). this internal clock is always the system cl ock of the attiny15l. this oscillator can be calibrated by writing the calibration byte (see page 55) to the osccal register. the system clock oscillator calibration register ? osccal writing the calibration byte to this address will trim the internal oscillator frequency in order to remove process variations. when osccal is zero (initial value), the lowest available frequency is chosen. writing non-zero values to this register will increase the frequency of the internal oscilla tor. writing $ff to the regist er selects the highest avail- able frequency. internal pll for fast peripheral clock generation the internal pll in attiny15l generates a clock frequency that is 16x multiplied from the rc oscillator system clock. if the rc oscillator frequency is the nominal 1.6 mhz, the fast peripheral clock is 25.6 mhz. the fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for timer/counter1. the pll is locked on the tu nable internal rc oscillator and adjusti ng the tunable inter- nal rc oscillator via the osccal register will adjust the fast peripheral clock at the same time. timer1 may malfun ction if the intern al rc oscillator is adjusted beyond 1.75 mhz. it is recommended not to take the osccal adjustments to a higher frequency than 1.75 mhz in order to keep proper operation of all chip functions. bit 76543210 $31 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 25 attiny15l 1187h?avr?09/07 timer/counters the attiny15l provides two general purpose 8-bit timer/counters. the timer/counters have separate prescaling selection from separate 10-bit prescalers. the timer/counter0 uses internal clock (ck) as the clock time base. the timer/counter1 may use either the internal clock (ck) or t he fast peripheral clock (pck) as the clock time base. the timer/counter0 prescaler figure 18 shows the timer/counter prescaler. figure 18. timer/counter0 prescaler the four prescaled selections are: ck/8, ck/64, ck/256, and ck/1024, where ck is the oscillator clock. ck, external source and st op, can also be selected as clock sources. setting the psr10 bit in sfior resets the pres caler. this allows the user to operate with a predictable prescaler. the timer/counter1 prescaler figure 19 shows the timer/counter1 prescaler. for timer/counter1 the clock selections are: pck, pck/2, pck/4, pck/8, ck (=pck/16), ck/2, ck/4, ck/8,ck/16, ck/32, ck/64, ck/128, ck/256, ck/512, ck/1024, and stop. the clock options are described in table 12 on page 31 and the timer/counter1 control register (tccr1). setting the psr1 bit in the sfior register resets the 10-bit prescaler. this allows the user to oper- ate with a predictable prescaler. figure 19. timer/counter1 prescaler 10-bit t/c prescaler 0 timer/counter0 clock source ck t0 psr0 clear cs00 tck0 cs01 cs02 ck/8 ck/256 ck/1024 ck/64 10-bit t/c prescaler timer/counter1 clock source ck psr1 cs10 cs11 cs12 ck/8 ck/256 ck/1024 ck/64 pck (25.6 mhz) (1.6 mhz) 0 cs13 clear clear 3-bit t/c prescaler pck/2 pck/4 pck/8 ck (=pck/16) ck/2 ck/4 ck/16 ck/32 ck/128 ck/512 26 attiny15l 1187h?avr?09/07 the special function io register ? sfior ? bit 7..3 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. ? bit 2 ? foc1a: force output compare 1a writing a logical ?1? to this bit forces a change in the compare match output pin pb1 (oc1a) according to the values already set in com1a1 and com1a0. the force out- put compare bit can be used to change the output pin without waiting for a compare match in timer. the automatic action programmed in com1a1 and com1a0 happens as if a compare match had occurred, but no interrupt is generated and the timer/counter1 will not be cleared even if ctc1 is set. the foc1a bit will always be read as zero. the setting of the foc1a bit has no effect in pwm mode. ? bit 1 ? psr1: prescaler reset timer/counter1 when this bit is set (one) the timer/counte r1 prescaler will be reset. the bit will be cleared by hardware after the operation is pe rformed. writing a ?0? to this bit will have no effect. this bit will always be read as zero. ? bit 0 ? psr0: prescaler reset timer/counter0 when this bit is set (one) the timer/counte r0 prescaler will be reset. the bit will be cleared by hardware after the operation is pe rformed. writing a ?0? to this bit will have no effect. this bit will always be read as zero. the 8-bit timer/counter0 figure 20 shows the block diagram for timer/counter0. the 8-bit timer/counter0 can select clock source from ck, prescaled ck or an external pin. in addition, it can be stopped as de scribed in the specification for the timer/counter0 control register (tccr0). th e overflow status flag is found in the timer/counter interrupt flag register (tifr). control signals are found in the timer/counter0 control register (tccr0). the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask register (timsk). when timer/counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to ensure proper samp ling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. si milarly, the high-prescaling opportunities make the timer/counter0 useful for lower-speed functions or exact-timing functions with infrequent actions. bit 76543210 $2c ?????foc1apsr1psr0sfior read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 27 attiny15l 1187h?avr?09/07 figure 20. timer/counter0 block diagram the timer/counter0 control register ? tccr0 ? bits 7..3 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. ? bits 2, 1, 0 ? cs02, cs01, cs00: clock select0, bits 2, 1 and 0 the clock select0 bits 2, 1 and 0 define the prescaling source of timer0. the stop condition provides a timer enable/disable function. the prescaled ck modes are scaled directly from the ck oscillator clock. if the exte rnal pin modes are used for timer/counter0, transitions on pb2/(t0) will cl ock the counter even if the pin is config- ured as an output. this feature can give the user sw control of counting. ocie1a toie1 toie0 tov0 tov0 cs02 cs01 cs00 tov1 ocf1a t/c clk source bit 76543210 $33 ? ? ? ? ? cs02 cs01 cs00 tccr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 9. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, the timer/counter0 is stopped. 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge 28 attiny15l 1187h?avr?09/07 the timer counter 0 ? tcnt0 the timer/counter0 is implemented as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues counting in the timer clock cycle following the write operation. the 8-bit timer/counter1 this module features a high-resolution and a high-accuracy usage with the lower pres- caling opportunities. timer/counter1 can also be used as an accurate, high speed, 8-bit pulse width modulator (pwm) using clock speeds up to 25.6 mhz. in this mode, timer/counter1 and the output compare registers serve as a standalone pwm. refer to page 34 for a detailed description of this function. similarly, the high-prescaling opportunities make this unit useful for lo wer-speed functions or exact-timing functions with infrequent actions. figure 21 shows the block diagram for timer/counter1. figure 21. timer/counter1 block diagram the two status flags (overflow and compare match) are found in the timer/counter interrupt flag register (tifr). control signals are found in the timer/counter control register (tccr1). the interrupt enable/disable settings are found in the timer/counter interrupt mask register (timsk). bit 76543210 $32 msb lsb tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 8-bit data bus timer int. flag register (tifr) timer/counter1 (tcnt1) 8-bit comparator t/c1 output t/c1 output compare register a compare register b timer int. mask register (timsk) t/c clear t/c1 control logic tov1 ocf1a ocf1a tov1 toie0 toie1 ocie1a ck pck t/c1 over- flow irq t/c1 a compare match irq t/c control register 1 (tccr1) cs12 com1a1 pwm1 cs11 com1a0 cs10 cs13 (ocr1a) 8-bit comparator (ocr1b) sfior tov0 foc1 psr1 ctc1 t/c1 oc1a pin/ port pb1 (pwm output) psr0 29 attiny15l 1187h?avr?09/07 the timer/counter1 contains two output compare registers, ocr1a and ocr1b, as the data source to be compared with the timer/counter1 contents. in normal mode the output compare function is operational with ocr1a only, and the output compare function includes optional clearing of the counter on compare match, and action on the output compare pin (pb1) (oc1a). in pwm mode ocr1a provides the data valu e against which the timer/counter value is compared. upon compare match the pwm output is generated. in pwm mode the timer/counter counts up to the value specified in output compare register ocr1b and starts again from $00. this feature allows limiting the counter ?full? value to a speci- fied value, lower than $ff. however, if ocr1n is $00, the output will remain constant and not toggle at all. if ocr1n equals $01, t he pulse width will be two ticks, increasing linearly if ocr1n is larger than $01. together with the many prescaler options, flexible pwm frequency selection is provided. table 14 lists clock selection and ocr1b values to obtain pwm frequencies from 10 khz to 150 khz at 10 khz steps. in applications with variable pwm, halving the prescaler setting and doubling the duty cycle can be used to fine-tune the pwm. alternatively inverted pwm can be used. the timer/counter1 control register ? tccr1 ? bit 7 ? ctc1: clear timer/counter on compare match when the ctc1 control bit is set (one), time r/counter1 is reset to $00 in the cpu clock cycle after a compare match with ocr1a register value. if the control bit is cleared, timer/counter1 continues counting and is unaffected by a compare match. ? bit 6 ? pwm1: pulse width modulator enable when set (one), this bit enables pwm mode for timer/counter1. this mode is described on page 31. ? bits 5,4 ? com1a1, com1a0: compare output mode, bits 1 and 0 the com1a1 and com1a0 control bits determine any output pin action following a compare match a in timer/counter1. output pin actions affect pin pb1(oc1a). since this is an alternative function to an i/o port, the corresponding direction control bit must be set (one) to control an output pin. the control configuration is shown in table 10. note: 1. in pwm mode, these bits have a different function. refer to table 12 for a detailed description.when changing the com1a1/com1a0 bits, the output compare 1a interrupt must be disabled by clearing its interrupt enable bit in the timsk register. otherwise an interrupt can occur when the bits are changed. bit 7 6 5 4 3 2 1 0 $30 ctc1 pwm1 com1a1 com1a0 cs13 cs12 cs11 cs10 tccr1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 10. compare mode select (1) com1a1 com1a0 description 0 0 timer/counter disconnected from output pin oc1a 0 1 toggle the oc1a output line. 1 0 clear the oc1a output line (to zero). 1 1 set the oc1a output line (to one). 30 attiny15l 1187h?avr?09/07 ? bits 3, 2, 1, 0 ? cs13, cs12, cs11, cs10: clock select bits 3, 2, 1, and 0 the clock select bits 3, 2, 1, and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable function. the prescaled ck modes are scaled directly from the ck oscillator clock. the timer/counter1 ? tcnt1 this 8-bit register contains the value of timer/counter1. timer/counter1 is implemented as an up-counter with read and write access. due to synchronization of the cpu and timer/counter1, data written into timer/counter1 is delayed by one cpu clock cycle. table 11. timer/counter1 prescale select cs13 cs12 cs11 cs10 description 0000timer/counter1 is sto pped. 0001ck*16 (=pck) 0010ck*8 (=pck/2) 0011ck*4 (=pck/4) 0100ck*2 (=pck/8) 0101ck 0110ck/2 0111ck/4 1000ck/8 1001ck/16 1010ck/32 1011ck/64 1100ck/128 1101ck/256 1110ck/512 1111ck/ 1024 bit 76543210 $2f msb lsb tcnt1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 31 attiny15l 1187h?avr?09/07 timer/counter1 output compare registera ? ocr1a the output compare register 1a is an 8-bit read/write register. the timer/counter output compare register 1a contains the data to be continuously compared with timer/count er1. actions on compare matc hes are specified in tccr1. a compare match occurs only if timer/counter1 counts to the ocr1a value. a software write that sets tcnt1 and ocr1a to the same value does not generate a compare match. a compare match will set (one) the compare interrupt flag in the cpu clock cycle fol- lowing the compare event. timer/counter1 in pwm mode when the pwm mode is selected, timer/counter1 and the output compare register a (ocr1a) form an 8-bit, free-running and glitch-free pwm with outputs on the pb1(oc1a) pin. timer/counter1 acts as an up-counter, counting up from $00 up to the value specified in the second output compare register ocr1b, and starting from $00 up again. when the counter value matches the contents of the output compare regis- ter ocr1a, the pb1(oc1a) pin is set or cleared according to the settings of the com1a1/com1a0 bits in the timer/counter1 control registers tccr1. refer to table 12 for details. note that in pwm mode, writing to the output compare ocr1a, the data value is first transferred to a temporary location. the value is latched into ocr1a when the timer/counter reaches ocr1b. this prev ents the occurrence of odd-length pwm pulses (glitches) in the event of an unsynchronized ocr1a write. see figure 22 for an example. bit 76543210 $2e msb lsb ocr1a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 12. compare mode select in pwm mode com1a1 com1a0 effect on compare pin 0 0 not connected 0 1 not connected 10 cleared on compare match (up-counting) (non-inverted pwm). set when tcnt1 = $00. 11 set on compare match (up-countin g) (inverted pwm). cleared when tcnt1 = $00. 32 attiny15l 1187h?avr?09/07 figure 22. effects of unsynchronized ocr latching during the time betwe en the write and the latch operat ion, a read from ocr1a will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1a. when ocr1a contains $00 or the top value, as specified in ocr1b register, the output pb1(oc1a) is held low or high according to the settings of com1a1/com1a0. this is shown in table 13. timer/counter1 output compare registerb ? ocr1b the output compare register1 (ocr1b) is an 8- bit read/write register. this register is used in the pwm mode only, and it limits the top value to which the timer/counter1 keeps counting. after reaching ocr1b in pwm mode, the counter starts from $00. in pwm mode, the timer overflow flag (tov1) is set as in normal timer/counter mode. timer overflow interrupt1 operates exactly as in normal timer/counter mode, i.e., it is executed when tov1 is set provided that timer overflow interrupt and global interrupts are enabled. this also applies to the timer output compare a flag and interrupt. pwm output oc1a pwm output oc1a unsynchronized oc1a latch synchronized oc1a latch counter value compare value counter value compare value compare value changes glitch compare value changes bit 76543210 $2d msb lsb ocr1b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 table 13. pwm outputs when ocr1a = $00 or ocr1b com1a1 com1a0 ocr1b output pwmn 10$00 l 1 0 ocr1b h 11$00 h 1 1 ocr1b l 33 attiny15l 1187h?avr?09/07 the frequency of the pwm will be timer clock frequency di vided by ocr1b value + 1. the exact duty-cycle of the non-inverted pwm output is: where: t t1 is the period of the selected timer/counter1 clock source. t pck is the period of the pck clock (39.1 ns). table 14. timer/counter1 clock prescale select clock selection ocr1b pwm frequency ck 159 10 khz pck/8 159 20 khz pck/4 213 30 khz pck/4 159 40 khz pck/2 255 50 khz pck/2 213 60 khz pck/2 181 70 khz pck/2 159 80 khz pck/2 141 90 khz pck 255 100 khz pck 231 110 khz pck 213 120 khz pck 195 130 khz pck 181 140 khz pck 169 150 khz ocr1a +1 () t t 1 t pck ? ocr1b +1 () t t 1 -------------------------------------------------------------------- - 34 attiny15l 1187h?avr?09/07 the watchdog timer the watchdog timer is clocked from a separate on-chip oscillator that runs at 1 mhz. this is the typical value at v cc = 5v. see ?typical characteristics? on page 66 for typical values at other v cc levels. by controlling the watc hdog timer prescaler, the watchdog reset interval can be adjusted from 16 to 2,048 ms, as shown in table 15. the wdr (watchdog reset) instruction resets the watchdog timer. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the attiny15l resets and executes from the reset vector. for timing details on the watchdog reset, refer to page 17. to prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. refer to the description of the watchdog timer control register for details. figure 23. watchdog timer the watchdog timer control register ? wdtcr ? bits 7..5 ? res: reserved bits these bits are reserved bits in the attiny15l and will always read as zero. ? bit 4 ? wdtoe: watchdog turn-off enable this bit must be set (one) when the wde bit is cleared. otherwise, the watchdog will not be disabled. once set, hardware will clear this bit to zero after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. ? bit 3 ? wde: watchdog enable when the wde is set (one), the watchdog timer is enabled and if the wde is cleared (zero), the watchdog timer function is disabled. wde can be cleared only when the wdtoe bit is set (one). to disable an enabled watchdog timer, the following proce- dure must be followed: 1 mhz at vcc = 5v 350 khz at vcc = 3v watchdog prescaler watchdog oscillator reset wdp0 wdp1 wdp2 wde mcu reset bit 76543210 $21 ? ? ? wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 35 attiny15l 1187h?avr?09/07 1. in the same operation, write a logical ?1? to wdtoe and wde. a logical ?1? must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logical ?0? to wde. this disables the watchdog. ? bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer prescaler bits 2, 1, and 0 the wdp2, wdp1 and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown in table 15. table 15. watchdog timer prescale select wdp2 wdp1 wdp0 time-out period 0 0 0 16k cycles 0 0 1 32k cycles 0 1 0 64k cycles 0 1 1 128k cycles 1 0 0 256k cycles 1 0 1 512k cycles 1 1 0 1,024k cycles 1 1 1 2,048k cycles 36 attiny15l 1187h?avr?09/07 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time is in the range of 4.6 - 8.2 ms, depending on the frequency of the calibrated rc oscillator. see table 16 for details. a self-timing function however, lets the user software detect when the next byte can be written. if the user code contains code that writes the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. cpu operation under th ese conditions is likely to cause the program counter to perform unintentional jumps and eventually execute the eeprom write code. to secure eeprom integrity, th e user is advised to use an external under- voltage reset circuit in this case. in order to prevent unintentional eeprom writes, a two-state write procedure must be followed. refer to the description of the eep rom control register for details of this. when the eeprom is read or written, the cp u is halted for two clock cycles before the next instruction is executed. the eeprom address register ? eear ? bit 7, 6 ? res: reserved bits these bits are reserved bits in the attiny15l and will always read as zero. ? bit 5..0 ? eear5..0: eeprom address the eeprom address register (eear) specifies the eeprom address in the 64 bytes eeprom space. the eeprom data bytes are addresses linearly between 0 and 63. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. the eeprom data register ? eedr ? bit 7..0 ? eedr7..0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address gi ven by the eear register. for the eeprom read oper- ation, the eedr contains the data read out from the eeprom at the address given by eear. bit 76543210 $1e ? ? eear5 eear4 eear3 eear2 eear1 eear0 eear read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x x x x x bit 76543210 $1d msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 37 attiny15l 1187h?avr?09/07 the eeprom control register ? eecr ? bit 7..4 ? res: reserved bits these bits are reserved bits in the attiny15l and will always read as zero. ? bit 3 ? eerie: eeprom ready interrupt enable when the i-bits in sreg and eerie are set (one), the eeprom ready interrupt is enabled. when cleared (zero), the interrupt is disabled. the eeprom ready interrupt generates a constant interrupt when eewe is cleared (zero). ? bit 2 ? eemwe: eeprom master write enable the eemwe bit determines w hether setting eewe to one causes the eeprom to be written. when eemwe is set (one), setting eewe will write data to the eeprom at the selected address. if eemwe is zero, setti ng eewe will have no effect. when eemwe has been set (one) by so ftware, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for an eeprom write procedure. ? bit 1 ? eewe: eeprom write enable the eeprom write enable signal ? eewe ? is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be set to write the value in to the eeprom. the eemwe bit must be set when the logical ?1? is written to eewe, oth- erwise no eeprom write takes place. t he following procedure should be followed when writing the eeprom (the order of steps 2 and 3 is not essential): 1. wait until eewe becomes zero. 2. write new eeprom addr ess to eear (optional). 3. write new eeprom data to eedr (optional). 4. write a logical ?1? to the eemwe bit in eecr. 5. within four clock cycles after setting eemwe, write a logical ?1? to eewe. caution: an interrupt be tween step 4 and step 5 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting an other eeprom access , the eear or eedr register will be modified, causing the interrupted eeprom ac cess to fail. it is recommended to have the global interrupt flag cleared during the four last steps to avoid these problems. when the write access time (typically 5.1 ms if the internal rc oscillator is calibrated to 1.6 mhz) has elapsed, the eewe bit is cleared (zero) by hardware. the user software can poll this bit and wait for a zero bef ore writing the next byte. when eewe has been set, the cpu is halted for two cycles be fore the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read st robe to the eeprom. when the correct address is set up in the eear register, the eere bit must be set. when the eere bit is cleared (zero) by hardware, requested data is found in the eedr register. the eeprom read access takes one instruction and there is no need to poll the eere bit. when eere has been set, the cpu is halted for four cycles before the next instruc- tion is executed. bit 76543 2 10 $1c ? ? ? ? eerie eemwe eewe eere eecr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 x 0 38 attiny15l 1187h?avr?09/07 the user should poll the eewe bit before starting the read operation. if a write operation is in progress when new data or address is written to the eeprom i/o registers, the write operation will be in terrupted and the re sult is undefined. the calibrated oscillator is us ed to time eeprom. in table 16 the typical programming time is listed for eeprom access from the cpu. preventing eeprom corruption during periods of low v cc , the eeprom data can be corrupte d because the supply volt- age is too low for the cpu and the eeprom to operate prope rly. these issues are the same as for board-level systems using th e eeprom and the same design solutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the eeprom requires a minimum voltage to operate correctly. second, the cpu itself can execute instructions incorrectly if the sup- ply voltage for executing instructions is too low. eeprom data corruption can easily be avoi ded by following thes e design recommen- dations (one is sufficient): 1. keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be applied. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to de code and execute instructions, effec- tively protecting the eeprom registers from unintentional writes. 3. store constants in flash memory if the ability to change memory contents from software is not required. flash memory cannot be up dated by the cpu and will not be subject to corruption. table 16. typical eeprom programming times parameter number of calibrated rc oscillator cycles min programming time max programming time eeprom write (from cpu) 8192 4.6 ms 8.2 ms 39 attiny15l 1187h?avr?09/07 the analog comparator the analog comparator compares the input values on the positive pin pb0 (ain0) and negative pin pb1 (ain1). when the voltage on the positive pin pb0 (ain0) is higher than the voltage on the negative pin pb1 (ain1), the analog comparator output (aco) is set (one). the comparator?s output can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 24 . figure 24. analog comparator block diagram the analog comparator control and status register ? acsr ? bit 7 ? acd: analog comparator disable when this bit is set (one), the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog comparator. this will reduce power con- sumption in active and idle mode. when changing the acd-bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap voltag e of 1.22 0.05v replaces the normal input to the positive pin (ain0) of the comparat or. when this bit is cleared, the normal input pin pb0 is applied to the positive pin of the comparator. ? bit 5 ? aco: analog comparator output aco is directly connected to the comparator output. ? bit 4 ? aci: analog comparator interrupt flag this bit is set (one) when a comparator output event triggers the interrupt mode defined by aci1 and aci0. the analog comparator in terrupt routine is executed if the acie bit is set (one) and the i-bit in sreg is set (one ). aci is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logical ?1? to the flag. bit 76543210 $08 acd acbg aco aci acie ? acis1 acis0 acsr read/write r/w r/w r r/w r/w r r/w r/w initial value 0 0 x 0 0 0 0 0 40 attiny15l 1187h?avr?09/07 ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is set (one) and the i-bit in the status register is set (one), the ana- log comparator interrupt is activated. when cleared (zero), the interrupt is disabled. ? bit 2 ? res: reserved bit this bit is a reserved bit in the at tiny15l and will alwa ys read as zero. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine the comparator events that trigger the analog comparator inter- rupt. the different settings are shown in table 17. note: 1. when changing the acis1/acis0 bits, the analog comparator interrupt must be dis- abled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. table 17. acis1/acis0 settings (1) acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on falling output edge 1 1 comparator interrupt on rising output edge 41 attiny15l 1187h?avr?09/07 the analog-to-digital converter, analog multiplexer, and gain stages features ? 10-bit resolution ? 2 lsb absolute accuracy ? 0.5 lsb integral non-linearity ? optional offset cancellation ? 65 - 260 s conversion time ? up to 15 ksps ? 4 multiplexed single-ended input channels ? 1 differential input channel with optional gain of 20x ? 2.56v internal voltage reference ? 0 - 2.56v differential input voltage range ? 0 - v cc single-ended input voltage range ? optional left adjustment for adc result readout ? free running or single conversion mode ? interrupt on adc co nversion complete ? sleep mode noise canceler the attiny15l features a 10-bit successive approximation adc. the adc is connected to a 4-channel analog multiple xer that allows one differential voltage input and four sin- gle-ended voltage inputs constructed from the pins of port b. the differential input (pb3, pb4) is equipped with a programmable gain stage, providing amplification step of 26 db (20x) on the differential input voltage before the a/d conversion. the single-ended volt- age inputs at pb2..pb5 refer to 0v (gnd). the adc contains a sample and hold amplifier that ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 25. an internal reference voltage of nominally 2.56v is provided on-chip and this reference can optionally be externally decoupled at the aref (pb0) pin by a capacitor for better noise performance. alternatively, v cc can be used as reference voltage for single- ended channels. there is also an option to use an external voltage reference and turn off the internal voltage reference. these op tions are selected using the refs1..0 bits of the admux control register. 42 attiny15l 1187h?avr?09/07 figure 25. analog-to-digital converter block schematic operation the adc converts an analog input voltage to a 10-bit digital value through successive approximation. the minimum value represents gnd and the maximum value represents the selected reference voltage minus 1 lsb. the voltage reference for the adc may be sele cted by writing to the refs1..0 bits in admux. v cc , the aref pin, or an internal 2.56v reference may be selected as the adc voltage reference. optionally, the 2.56v internal voltage reference may be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and differential gain are selected by writing to the mux2..0 bits in admux. any of the four adc input pins adc3..0 can be selected as single- ended inputs to the adc. adc2 and adc3 can be selected as positive and negative input, respectively, to the differential gain amplifier. if differential channels are selected, the differential gain stage amplifies the voltage dif- ference between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of the mux2..0 bits in ad mux. this amplified value then becomes the analog input to the adc. if single-ended channels are used, the gain amplifier is bypassed altogether. if adc2 is selected as both the positive and negative input to the differential gain ampli- fier (adc2 - adc2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. this figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 lsb. the adc can operate in two modes ? single conversion and free running. in single conversion mode, each conver sion will have to be initiated by the user. in free running adc conversion complete irq 8-bit data bus 90 adc multiplexer select (admux) adc ctrl. & status register (adcsr) adc data register (adch/adcl) mux2 adie adfr adsc aden adif adif mux1 mux0 adps0 adps1 adps2 conversion logic 10-bit dac + - sample & hold comparator internal 2.56 v reference mux decoder vcc aref adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] gain amplifier prescaler single ended / differential selection pos. input mux neg. input mux 43 attiny15l 1187h?avr?09/07 mode, the adc is constantly sampling and updating the adc data register. the adfr bit in adcsr selects between the two available modes. the adc is enabled by setting the adc enable bit, aden in adcsr. voltage reference and input channel select ions will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power-saving sleep modes. a conversion is started by writing a logical ?1? to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in prog ress and will be set to zero by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will fi nish the current conver sion before performing the channel change. the adc generates a 10-bit result, which is presented in the adc data registers, adch and adcl. by default, the result is presented right-adjusted, but can optionally be presented left-adjusted by setting the adlar bit in admux. if the result is left-adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read fi rst, then adch, to en sure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the con- version is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt, which c an be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if t he result is lost. prescaling and conversion timing figure 26. adc prescaler the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz. using a higher input fr equency will affect the conversion accuracy, see ?adc characteristics? on page 50. the adc module contains a prescaler, which divides the system clock to an acceptable adc clock frequency. the adpsn bits in adcsr are used to generate a proper adc clock input frequency from any ck frequency above 100 khz. the prescaler starts counting from the moment 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden 44 attiny15l 1187h?avr?09/07 the adc is switched on by setting the aden bit in adcsr. the prescaler keeps running for as long as the aden bit is set, an d is continuously reset when aden is low. when initiating a conversion by setting the ad sc bit in adcsr, the conversion starts at the following rising edge of the adc clock cycle. if differential channels are selected, the conversion will only start at every other rising edge of the adc clock cycle after aden was set. a normal conversion takes 13 adc clock cycle s. in certain situations, the adc needs more clock cycles to perform initializati on and minimize offset errors. these extended conversions take 25 adc clock cycles and occu r as the first conversion after one of the following events: ? the adc is switched on (aden in adcsr is set). ? the voltage reference source is changed (the refs1..0 bits in admux change value). ? a differential channel is selected (mux2 in admux is ?1?). note that subsequent conversions on the same channel are not extended conversions. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 13.5 adc clock cycles after the start of an extended conversion. when a conversion is complete, the result is written to the adc data registers, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initiated on the fi rst rising adc clock edge. in free running mode, a new conversion will be started immediately after the conversion completes while adsc remains high. using free running mode and an adc clock frequency of 200 khz gives the lowest conversion time, 65 s , equivalent to 15 ksps. for a summ ary of conversion ti mes, see table 18. figure 27. adc timing diagram, first conver sion (single conversion mode) sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 extended conversion next conversion 3 mux and refs update mux and refs update conversion complete 45 attiny15l 1187h?avr?09/07 figure 28. adc timing diagram, single conversion figure 29. adc timing diagram, free running conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 extended conversion next conversion 3 mux and refs update mux and refs update conversion complete table 18. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) conversion time (s) extended conversion 13.5 25.0 125 - 500 normal conversions 1.5 13.0 65 - 260 11 12 13 sign and msb of result lsb of result a dc clock a dsc a dif a dch a dcl c ycle number 12 one conversion next conversion 34 conversion complete sample & ho ld mux and refs update 46 attiny15l 1187h?avr?09/07 adc noise canceler function the adc features a noise canceler that enables conversion during adc noise reduc- tion mode (see ?sleep modes? on page 23) to reduce noise induced from the cpu core and other i/o peripherals. if other i/o peripher als must be active during conversion, this mode works equivalently for idle mode. to make use of this feature, the following proce- dure should be used: 1. make sure that the adc is enabled and is not busy converting. single conver- sion mode must be selected and the adc conversion complete interrupt must be enabled. aden = 1 adsc = 0 adfr = 0 adie = 1 2. enter adc noise reduction mode (or id le mode). the adc will start a conver- sion once the cpu has been halted. 3. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the mcu and execute th e adc conversion complete interrupt routine. the adc multiplexer selection register ? admux ? bits 7..6 ? refs1..refs0: reference selection bits these bits select the voltage reference for the adc, as shown in table 19. if these bits are changed during a conversion , the change will not go into effect until this conversion is complete (adif in adcsr is set). whenever these bits are changed, the next conversion will take 25 adc clock cycles. if active channels are used, using avcc or an external aref higher than (avcc - 1v) is not recommended, as this will affect adc accuracy. the internal voltage reference options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. if adlar is cleared, the result is ri ght-adjusted. if adlar is set, the result is left-adjusted. changing the adlar bit will affect the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see ?the adc data register ? adcl and adch? on page 49. bit 76543210 $07 refs1 refs0 adlar ? ? mux2 mux1 mux0 admux read/write r/w r/w r/w r r r/w r/w r/w initial value00000000 table 19. voltage reference selections for adc refs1 refs0 voltage reference selection 00v cc used as analog reference, disconnected from pb0 (aref). 01 external voltage reference at pb0 (aref) pin, internal voltage reference turned off. 10 internal voltage reference without external bypass capacitor, disconnected from pb0 (aref). 11 internal voltage reference with external bypass capacitor at pb0 (aref) pin. 47 attiny15l 1187h?avr?09/07 ? bits 4..3 ? res: reserved bits these bits are reserved bits in the attiny15l and always read as zero. ? bits 2..0 ? mux2..mux0: analog channel and gain selection bits 2..0 the value of these bits selects which analog input is connected to the adc. in case of differential input (pb3 - pb4), gain selection is also made with these bits. selecting pb3 as both inputs to the differential gain stage enables offset measurements. refer to table 20 for details. if these bits are changed during a conversion, the change will not go into effect until this conversion is co mplete (adif in adcsr is set). note: 1. for offset calibration on ly. see ?operation? on page 42. the adc control and status register ? adcsr ? bit 7 ? aden: adc enable writing a logical ?1? to this bit enables the ad c. by clearing this bit to zero, the adc is turned off. turning the adc of f while a conversion is in progress will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, a logical ?1? must be written to this bit to start each conver- sion. in free running mode, a logical ?1? must be written to this bit to start the first conversion. when the conversion completes, adsc returns to zero in single conversion mode and stays high in free running mode. writing a ?0? to this bit has no effect. ? bit 5 ? adfr: adc free running select when this bit is set (one), the adc operates in free running mode. in this mode, the adc samples and updates the data registers continuously. clearing this bit (zero) will terminate free running mode. if active channels are used (mux2 in admux set), the table 20. input channel and gain selections mux2..0 single-ended input positive differential input negative differential input gain 000 adc0 (pb5) n/a 001 adc1 (pb2) 010 adc2 (pb3) 011 adc3 (pb4) 100 (1) n/a adc2 (pb3) adc2 (pb3) 1x 101 (1) adc2 (pb3) adc2 (pb3) 20x 110 adc2 (pb3) adc3 (pb4) 1x 111 adc2 (pb3) adc3 (pb4) 20x bit 76543210 $06 aden adsc adfr adif adie adps2 adps1 adps0 adcsr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 48 attiny15l 1187h?avr?09/07 channel must be selected before entering free running mode. selecting an active channel after entering free running mode may result in undefined operation from the adc. ? bit 4 ? adif: adc interrupt flag this bit is set (one) when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i- bit in sreg are set (one). adif is clea red by hardware when executing the correspond- ing interrupt handling vector. alte rnatively, adif is cleared by writing a logical ?1? to the flag. beware that if doing a read-modify-write on adcsr, a pending interrupt can be dis- abled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is set (one) and the i-bit in sreg is set (one), the adc conversion com- plete interrupt is activated. ? bits 2..0 ? adps2..adps0: adc prescaler select bits these bits determine the division factor between the ck frequency and the input clock to the adc. see table 21. table 21. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 49 attiny15l 1187h?avr?09/07 the adc data register ? adcl and adch adlar = 0 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated until adch is read. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be re ad first, then adch. the adlar bit in admux affects the way the result is read from the registers. if adlar is set, the result is left-adjusted. if adlar is cleared (default), the result is right-adjusted. ? adc9..0: adc conversion result these bits represent the result from the conversion. for the differential channel, this is the value after gain adjustment, as indicated in table 20 on page 47. for single-ended conversion, or if adlar or sign is zero, $000 represents ground and $3ff represents the selected reference voltage minus one lsb. scanning multiple channels since change of analog channel always is delayed until a conversion is finished, the free running mode can be used to scan multiple channels without interrupting the con- verter. typically, the adc conversion comp lete interrupt will be used to perform the channel shift. however, the user should take the following fact into consideration: the interrupt triggers once the result is ready to be read. in free running mode, the next conversion will start immediately when the interrupt triggers. if admux is changed after the interrupt triggers, the next conversion has already started, and the old setting is used. bit 151413121110 9 8 $05 ? ? ? ? ? ? adc9 adc8 adch $04 adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 $05 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch $04 adc1 adc0 ? ????? adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 50 attiny15l 1187h?avr?09/07 adc noise-canceling techniques digital circuitry inside and outside the attiny 15l generates emi, which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. the analog part of the attiny15l and all analog components in the application should have a separate analog ground plane on the pcb. this ground plane is connected to the digital ground plane via a single point on the pcb. 2. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 3. use the adc noise canceler function to reduce induced noise from the cpu. 4. if some port b pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. adc characteristics symbol parameter condition min typ max units resolution single-ended conversion 10.0 bits differential conversion gain = 1x or 20x 8.0 bits absolute accuracy single-ended conversion v ref = 4v adc clock = 200 khz 1.0 2.0 lsb single-ended conversion v ref = 4v adc clock = 1 mhz 4.0 lsb single-ended conversion v ref = 4v adc clock = 2 mhz 16.0 lsb integral non-linearity v ref > 2v 0.5 lsb differential non-linearity v ref > 2v 0.5 lsb zero error (offset) v ref > 2v 1.0 lsb conversion time free running conversion 65.0 260.0 s clock frequency 50.0 200.0 khz v ref reference voltage single-ended conversion 2.0 v cc v differential conversion 2.0 v cc - 0.2 v v int internal voltage reference 2.4 2.56 2.7 v r ref reference input resistance 6.0 10.0 13.0 k r ain analog input resistance 100.0 m 51 attiny15l 1187h?avr?09/07 i/o port b all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintention- ally changing the direction of any other pin with the sbi and cbi instructions. the same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). port b is a 6-bit bi-directional i/o port. three data memory address locations are allocated for port b, one each for the data register ? portb, $18, data direction register ? ddrb, $17, and the port b input pins ? pinb, $16. the port b input pins address is read-only, while the data register and the data direction register are read/write. ports pb5..0 have special functions as described in the section ?pin descriptions? on page 4. if pb5 is not configured as external reset, it is input with no pull-up or as an open-drain output. all i/o pins have individua lly selectable pull-ups, which can be over- ridden with pull-up disable. the port b output buffers on pb0 to pb4 can sink 20 ma and thus drive led displays directly. pb5 can sink 12 ma. when pins pb0 to pb4 are used as inputs and are exter- nally pulled low, they will source current (i il ) if the internal pull-ups are activated. unconnected pins if some pins are unused, it is recommended to ensure that these pins have a defined level. the simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. in this case, the pull-up w ill be disabled during reset. if low power con- sumption during reset is important, it is recommended to use an external pull-up or pull- down. connecting unused pins directly to vcc or gnd is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. alternative functions of port b in attiny15l four port b pins ? pb2, pb3, pb4, and pb5 ? have alternative functions as inputs for the adc. if some port b pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. this might corrupt the result of the conversion. during power-down mode and adc noise reduction mode, the schmitt triggers of the digital inputs are disconnected on these pins. this allows an analog input voltage close to v cc /2 to be present during power-down without causing excessive power consumption. the port b pins with al ternate functions are shown in table 1 on page 4. when the pins pb4..0 are used for the al ternate function, the ddrb and portb regis- ters have to be set according to the alternate function description. when pb5 is used as external reset pin, the values in the corresponding ddrb and portb bit are ignored. the port b data register ? portb the port b data direction register ? ddrb bit 76543210 $18 ? ? ? portb4 portb3 portb2 portb1 portb0 portb read/write r r r r/w r/ws r/w r/w r/w initial value00000000 bit 76543210 $17 ? ? ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 52 attiny15l 1187h?avr?09/07 the port b input pins address ? pinb the port b input pins address (pinb) is not a register, and this address enables access to the physical value on each port b pin. w hen reading portb, the portb data latch is read, and when reading pinb, the logical values present on the pins are read. port b as general digital i/o the lower five pins in port b are equal when used as digital i/o pins. pbn, general i/o pin: the ddbn bit in the ddrb register selects the direction of this pin. if ddbn is set (one), pbn is configured as an output pin. if ddbn is cleared (zero), pbn is configured as an input pin. if portbn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the portbn has to be cleared (zero) or the pin has to be configured as an output pin. pull- ups for all ports can be disabled also by setting pud-bit in the mcucr register. note: 1. n: 4, 3?0, pin number. on attiny15l, pb5 is input or open-drain out put. because this pin is used for 12v pro- gramming, there is no esd protection diode limiting the voltage on the pin to v cc + 0.5v. thus, special care should be taken to ensure that the voltage on this pin does not rise above v cc + 1v during normal operation. this may cause the mcu to reset or enter programming mode unintentionally. all port b pins are connected to a pin c hange detector that can trigger the pin change interrupt. see ?pin change interrupt? on page 22 for details. alternate functions of port b the alternate pin functions of port b are: ? reset ? port b, bit 5 when the rstdisbl fuse is unprogrammed, this pin serves as external reset. when the rstdisbl fuse is programmed, this pin is a general input pin or a open-drain out- put pin. if ddb5 is cleared (zero), pb5 is configured as an input pin. if ddb5 is set (one), the pin is a open-drain output. ? sck/int0/t0 ? port b, bit 2 in serial programming mode, this pin serves as the serial clock input, sck. in normal mode, this pin can serve as the external interrupt0 input. see the interrupt description for details on how to enable this inte rrupt. note that activity on this pin will trigger the interrupt even if the pin is configured as an output. bit 76543210 $16 ? ? pinb5 pinb4 pinb3 pi nb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value 0 0 n/a n/a n/a n/a n/a n/a table 22. ddbn effects on port b pins (1) ddbn portbn i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input no pud bit in the mcucr register is set. 0 1 input yes pbn will source current if ext. pulled low. pud bit in the mcucr register is cleared. 1 0 output no push-pull zero output 1 1 output no push-pull one output 53 attiny15l 1187h?avr?09/07 in normal mode, this pin can serve as t he external counter clock input. see the timer/counter0 description for further deta ils. if external timer/counter clocking is selected, activity on this pin will clock the counter even if it is configured as an output. ? miso/oc1a/ain1 ? port b, bit 1 in serial programming mode, this pin serves as the serial data output, miso. in normal mode, this pin can serve as timer/counter1 output compare match output (oc1a). see the timer/counter1 description for further details, and how to enable the output. the oc1a pin is also the output pin for pwm mode timer function. this pin also serves as the negative i nput of the on-chip analog comparator. ? mosi/ain0/aref ? port b, bit 0 in serial programming mode, this pin serves as the serial data input, mosi. in normal mode, this pin also serves as the positive input of the on-chip analog comparator. in attiny15l, this pin can be chosen to be the reference voltage for the adc. refer to the section ?the analog-to-digital converter, analog multiplexer, and gain stages? for details. 54 attiny15l 1187h?avr?09/07 memory programming program and data memory lock bits the attiny15l mcu provides two lock bits that can be left unprogrammed, ?1?, or can be programmed, ?0?, to obtain the additional features listed in table 23 . the lock bits can only be erased with the chip erase command . fuse bits the attiny15l has six fuse bits (b odlevel, boden, spien, rstdsbl, and cksel1..0). all the fuse bits are prog rammable in both high-voltage and low-voltage serial programming modes. changing the fuses does not have effect while in program- ming mode. ? the bodlevel fuse selects the brown-out detection le vel and changes the start- up times. see ?brown-out detection? on page 17. see table 5 on page 15. default value is programmed ?0?. ? when the boden fuse is programed ?0?, the brown-out detector is enabled. see ?brown-out detection? on page 17. default value is unprogrammed ?1?. ? when the spien fuse bit is programmed ?0?, low-voltage serial program and data downloading is enabled. default value is programmed ?0?. unprogramming this fuse while in the low-voltage se rial programming mode will disable future in-system downloading attempts. ? when the rstdisbl fuse is programmed ?0?, the external reset function of pin pb5 is disabled (1) . default value is unprogrammed ?1?. programming this fuse while in the low-voltage serial programming mode will di sable future in-system downloading attempts. ? cksel1..0 fuses: see table 5 on page 15 for which combination of cksel1..0 to use. default value is ?00?, 64 ms + 18 ck. the status of the fuse bits is not affected by chip erase. note: 1. if the rstdisbl fuse is programmed, then the programming hardware should apply +12v to pb5 while the attiny15l is in power-on reset. if not, the part can fail to enter programming mode caused by drive contention on pb0 and/or pb5. signature bytes all atmel microcontrollers have a three-byte signature code that identifies the device. the three bytes reside in a separate address space, and for the attiny15l they are: 1. $000 : $1e (indicates manufactured by atmel). 2. $001 : $90 (indicates 1 kb flash memory). 3. $002 : $06 (indicates attiny15l device when $001 is $90). table 23. lock bit protection modes memory lock bits protection type mode lb1 lb2 1 1 1 no memory lock features enabled. 2 0 1 further programming of the flash and eeprom is disabled. 3 0 0 same as mode 2, but verify is also disabled. 55 attiny15l 1187h?avr?09/07 calibration byte the attiny15l has a one-byte ca libration value for the internal rc o scillator. this byte resides in the high byte of address $000 in the signature address space. to make use of this byte, it should be read from this loca tion and written into the normal flash program memory. at start-up, the user software must read this flash location and write the value to the osccal register. programming the flash atmel?s attiny15l offers 1k byte of in-system reprogrammable flash program mem- ory and 64 bytes of in-system re programmable eeprom data memory. the attiny15l is shipped with the on-chip flash program and eeprom data memory arrays in the erased state (i.e., contents = $ff) and ready to be programmed. this device supports a high-voltage (12v) serial programming mode and a low-voltage serial programming mode. the +12v is used for programming enable only, and no cur- rent of significance is draw n by this pin (less than 100 a) . the low-voltage serial programming mode provides a convenient way to download program and data into the attiny15l inside the user?s system. the program and data memory arrays in the attiny15l are programmed byte-by-byte in either programming mode. for the eepr om, an auto-erase cycle is provided within the self-timed write instruction in the low-voltage serial programming mode. during programming, the supply voltage must be in accordance with table 24. high-voltage serial programming this section describes how to program and verify flash program memory, eeprom data memory, lock bits and fuse bits in the attiny15l. figure 30. high-voltage serial programming table 24. supply voltage during programming part low-voltage serial programming high-voltage serial programming attiny15l 2.7 - 5.5v 4.5 - 5.5v pb5 (reset) pb3 gnd vcc pb2 pb1 pb0 serial data output serial instr. input serial data input serial clock input 11.5 - 12.5v 4.5 - 5.5v attiny15/l 56 attiny15l 1187h?avr?09/07 high-voltage serial programming algorithm to program and verify the attiny15l in the high-voltage serial programming mode, the following sequence is recommended (see instruction formats in table 25): 1. power-up sequence: apply 4.5 - 5.5v between v cc and gnd. set pb5 and pb0 to ?0? and wait at least 30 s. set pb3 to ?0?. wait at least 100 ns. apply 12v to pb5 and wait at least 100 ns before changing pb0. wait 8 s before giving any instructions. 2. the flash array is programmed one byte at a time by supplying first the address, then the low and high data byte. the write instruction is self-timed; wait until the pb2 (rdy/bsy ) pin goes high. 3. the eeprom array is programmed one byte at a time by supplying first the address, then the data byte. the write inst ruction is self-timed; wait until the pb2 (rdy/bsy ) pin goes high. 4. any memory location can be verified by using the read instruction, which returns the contents at the selected address at serial output pb2. 5. power-off sequence: set pb3 to ?0?. set pb5 to ?0?. tu r n v cc power off. when writing or reading serial data to the attiny15l, data is clocked on the eigth rising edge of the 16 external clock pulses needed to generate the internal clock. see figure 31, figure 32, and table 26 for an explanation. figure 31. high-voltage serial programming waveforms msb msb msb lsb lsb lsb 012345678910 serial data input pb0 serial instr. input pb1 serial data output pb2 internal ck serial clock input pb3 16x 57 attiny15l 1187h?avr?09/07 table 25. high-voltage serial programming instruction set for attiny15l (1) instruction instruction format operation remarks instr.1 instr.2 instr.3 instr.4 chip erase pb0 pb1 pb2 0_1000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx wait after instr.3 until pb2 goes high for the chip erase cycle to finish. write flash high and low address pb0 pb1 pb2 0_0001_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_000 a _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 for a new 256 byte page. repeat instr.3 for each new address. write flash low byte pb0 pb1 pb2 0_ i i i i _ i i i i _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 0_0000_0000_00 wait after instr.3 until pb2 goes high. repeat instr.1, instr. 2 and instr.3 for each new address. write flash high byte pb0 pb1 pb2 0_ i i i i _ i i i i _00 0_0011_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 0_0000_0000_00 wait after instr.3 until pb2 goes high. repeat instr.1, instr. 2 and instr.3 for each new address. read flash high and low address pb0 pb1 pb2 0_0000_0010_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_000 a _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 and instr.3 for each new address. read flash low byte pb0 pb1 pb2 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 o _ oooo _ ooo x_xx repeat instr.1 and instr.2 for each new address. read flash high byte pb0 pb1 pb2 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 o _ oooo _ ooo x_xx repeat instr.1 and instr.2 for each new address. write eeprom low address pb0 pb1 pb2 0_0001_0001_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_00 bb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 for each new address. write eeprom byte pb0 pb1 pb2 0_ i i i i _ i i i i _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 0_0000_0000_00 wait after instr.3 until pb2 goes high read eeprom low address pb0 pb1 pb2 0_0000_0011_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_00 bb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 for each new address. read eeprom byte pb0 pb1 pb2 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 o _ oooo _ ooo x_xx repeat instr.2 for each new address write fuse bits pb0 pb1 pb2 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ 8765 _11 43 _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx wait after instr.4 until pb2 goes high. write 8 - 3 = ?0? to program the fuse bit. write lock bits pb0 pb1 pb2 0_0010_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0 21 0_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 0_0000_0000_00 wait after instr.4 until pb2 goes high. write 2 , 1 = ?0? to program the lock bit. read fuse bits pb0 pb1 pb2 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 8 _ 765 x_x 43 x_xx reading 8 - 3 = ?0? means the fuse bit is programmed. 58 attiny15l 1187h?avr?09/07 note: 1. a = address high bits b = address low bits i = data in o = data out x = don?t care 1 = lock bit1 2 = lock bit2 3 = cksel0 fuse 4 = cksel1 fuse 5 = rstdsbl fuse 6 = spien fuse 7 = boden fuse 8 = bodlevel fuse the lock bits can only be cleared by executing a chip erase. read lock bits pb0 pb1 pb2 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_ 21 xx_xx reading 2 , 1 = ?0? means the lock bit is programmed read signature bytes pb0 pb1 pb2 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_00 bb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 o _ oooo _ ooo x_xx repeat instr.2 - instr.4 for each signature byte address read calibration byte pb0 pb1 pb2 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 o _ oooo _ ooo x_xx table 25. high-voltage serial programming instruction set for attiny15l (1) (continued) instruction instruction format operation remarks instr.1 instr.2 instr.3 instr.4 59 attiny15l 1187h?avr?09/07 high-voltage serial programming characteristics figure 32. high-voltage serial programming timing low-voltage serial downloading both the program and data memory arrays can be programmed using the spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output). see fi gure 33. after reset is set low, the prog ramming enable instruc- tion needs to be executed first before program/erase instructions can be executed. figure 33. serial programming and verify for the eeprom, an auto-erase cycle is provided within the self-tim ed write instruction and there is no need to first execute the chip erase instruction. the chip erase instruc- tion turns the content of every memory location in both the program and eeprom arrays into $ff. the program and eeprom memory arrays ha ve separate addres s spaces: $0000 to $01ff for program memory and $000 to $03f for eeprom memory. table 26. high-voltage serial programming characteristics, t a = 25 c 10%, v cc = 5.0v 10% (unless otherwise noted) symbol parameter min typ max units t shsl sci (pb3) pulse width high 25.0 ns t slsh sci (pb3) pulse width low 25.0 ns t ivsh sdi (pb0), sii (pb1) valid to sci (pb3) high (8th edge) 50.0 ns t shix sdi (pb0), sii (pb1) hold after sci (pb3) high (8th edge) 50.0 ns t shov sci (pb3) high (9th edge) to sdo (pb2) valid 10.0 16.0 32.0 ns sdi (pb0), sii (pb1) sdo (pb2) sci (pb3) t ivsh t shsl t slsh t shix t shov internal ck 1 2 7 8 9 10 15 16 valid pb5 (reset) gnd vcc pb2 pb1 pb0 sck miso mosi 2.7 - 5.5v attiny15/l 60 attiny15l 1187h?avr?09/07 the device is clocked from the internal clock at the uncalibrated minimum frequency (0.8 - 1.6 mhz). the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 mcu clock cycles high: > 2 mcu clock cycles low-voltage serial programming algorithm when writing serial data to the attiny15l, data is clocked on the rising edge of sck. when reading data from the attiny15l, data is clocked on th e falling edge of sck. see figure 34, figure 35, and table 28 for timing details. to program and verify the attiny15l in the serial programming mode, the following sequence is recommended (see 4-byte instruction formats in table 27 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. if the pro- grammer cannot guarantee that sck is held low during power-up, reset must be given a positive pulse of at least two mcu cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the program- ming enable serial instruction to the mosi (pb0) pin. refer to the above section for minimum low and high periods for the serial clock input sck. 3. the serial programming instructions will not work if the communication is out of synchronization. when in sync, the seco nd byte ($53) will echo back when issu- ing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the $53 did not echo back, give sck a positive pulse and issue a new programming enable instruction. if the $53 is not seen within 32 attempts, there is no functional device connected. 4. if a chip erase is performed (must be done to erase the flash), wait t wd_erase after the instruction, give reset a positive pulse, and start over from step 2. see table 29 on page 63 for t wd_erase value. 5. the flash or eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate writ e instruction. an eeprom memory location is first automatically erased before new data is written. use data polling to detect when the next byte in the flash or eeprom can be written. if polling is not used, wait t wd_prog_fl or t wd_prog_ee , respectively, before trans- mitting the next instruction. see table 30 on page 63 for the t wd_prog_fl and t wd_prog_ee values. in an erased device, no $ffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction, which returns the content at the selected address at the serial output miso (pb1) pin. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn v cc power off. 61 attiny15l 1187h?avr?09/07 data polling when a byte is being programmed into the flash or eeprom, reading the address location being programmed will give the value $f f. at the time the device is ready for a new byte, the programmed value will read correctly. this is used to determ ine when the next byte can be written. this will not work for the value $ff so when programming this value, the user will have to wait for at least t wd_prog_fl before programming the next flash byte, or t wd_prog_ee before the next eeprom byte. as a chip-erased device con- tains $ff in all locations, programming of addresses that are meant to contain $ff can be skipped. this does not apply if the eeprom is reprogrammed without chip-erasing the device. in that ca se, data polling cannot be used fo r the value $ff and the user will have to wait at least t wd_prog_ee before programming the next byte. see table 30 for t wd_prog_fl and t wd_prog_ee values. figure 34. low-voltage serial programming waveforms msb msb lsb lsb serial clock input pb2(sck) serial data input pb0(mosi) serial data output pb1(miso) 62 attiny15l 1187h?avr?09/07 note: 1. a = address high bits b = address low bits h = 0 ? low byte, 1 ? high byte o = data out i = data in x = don?t care 1 = lock bit 1 2 = lock bit 2 3 = cksel0 fuse 4 = cksel1 fuse 5 = rstdisbl fuse 6 = spien fuse 7 = boden fuse 8 = bodlevel fuse table 27. low-voltage serial programming instruction set (1) instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming while reset is low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase flash and eeprom memory arrays. read program memory 0010 h 000 xxxx xxx a bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . write program memory 0100 h 000 xxxx xxx a bbbb bbbb iiii iiii write h (high or low) data i to program memory at word address a : b . read eeprom memory 1010 0000 xxxx xxxx xx bb bbbb oooo oooo read data o from eeprom memory at address b . write eeprom memory 1100 0000 xxxx xxxx xx bb bbbb iiii iiii write data i to eeprom memory at address b . write lock bits 1010 1100 1111 1 21 1 xxxx xxxx xxxx xxxx write lock bits. set bits 1,2 = ?0? to program lock bits. read lock bits 0101 1000 xxxx xxxx xxxx xxxx xxxx x 21 x read lock bits. ?0? = programmed, ?1? = unprogrammed. read signature bytes 0011 0000 xxxx xxxx 0000 00 bb oooo oooo read signature byte o at address b . write fuse bits 1010 1100 101x xxxx xxxx xxxx 8765 11 43 set bits 8 - 3 = ?0? to program, ?1? to unprogram. read fuse bits 0101 0000 xxxx xxxx xxxx xxxx 8765 xx 43 read fuse bits. ?0? = programmed, ?1? = unprogrammed. read calibration byte 0011 1000 xxxx xxxx 0000 0000 oooo oooo 63 attiny15l 1187h?avr?09/07 low-voltage serial programming characteristics figure 35. low-voltage serial programming timing table 28. low-voltage serial programming characteristics, t a = -40 c to 85 c, v cc = 2.7 - 5.5v (unless otherwise noted) symbol parameter min typ max units 1/t clcl rc oscillator frequency (v cc = 2.7 - 5.5v) 0.8 1.6 mhz t clcl rc oscillator period (v cc = 2.7 - 5.5v) 625.0 1250.0 ns t shsl sck pulse width high 2.0 t clcl ns t slsh sck pulse width low 2.0 t clcl ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2.0 t clcl ns t sliv sck low to miso valid 10.0 16.0 32.0 ns table 29. minimum wait delay after th e chip erase instruction symbol minimum wait delay t wd_erase 8.2 ms table 30. minimum wait delay after writ ing a flash or eeprom location symbol minimum wait delay t wd_flash 4.1 ms t wd_eeprom 8.2 ms m osi m iso sck t ovsh t shsl t slsh t shox t sl iv 64 attiny15l 1187h?avr?09/07 electrical characteristics absolute maximum ratings operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ............................. -1.0v to v cc + 0.5v voltage on reset with respect to ground ....-1.0v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 100.0 ma dc characteristics t a = -40 c to 85 c, v cc = 2.7v to 5.5v symbol parameter condition min typ max units v il input low voltage exce pt (xtal) -0.5 0.3 v cc (1) v v il1 input low voltage xtal -0.5 0.1 v cc (1) v v ih input high voltage except (xtal, reset ) 0.6 v cc (2) v cc + 0.5 v v ih1 input high voltage xtal 0.7 v cc (2) v cc + 0.5 v v ih2 input high voltage reset 0.85 v cc (2) v cc + 0.5 v v ol output low voltage (1) port b i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.6 0.5 v v v ol output low voltage pb5 i ol = 12 ma, v cc = 5v i ol = 6 ma, v cc = 3v 0.6 0.5 v v v oh output high voltage (4) port b i oh = -3 ma, v cc = 5v i oh = -1.5 ma, v cc = 3v 4.3 2.3 v v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 8.0 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 8.0 a r i/o i/o pin pull-up 35.0 122 k i cc power supply current active, v cc = 3v 3.0 ma idle, v cc = 3v 1.0 1.2 ma power-down (2) , v cc = 3v wdt enabled 9.0 15.0 a power-down (2) , v cc = 3v wdt disabled <1.0 2.0 a 65 attiny15l 1187h?avr?09/07 note: 1. ?max? means the highest value where the pin is guaranteed to be read as low. 2. ?min? means the lowest value where t he pin is guaranteed to be read as high. 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: 1] the sum of all i ol , for all ports, should not exceed 100 ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 4. although each i/o port can source more than the test conditions (3 ma at v cc = 5v, 1.5 ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: 1] the sum of all i oh , for all ports, should not exceed 100 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 5. minimum v cc for power-down is 1.5v (only with bod disabled). v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 40.0 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50.0 50.0 na t acid analog comparator initialization delay v cc = 2.7v v cc = 4.0v 750.0 500.0 ns dc characteristi cs (continued) t a = -40 c to 85 c, v cc = 2.7v to 5.5v symbol parameter condition min typ max units 66 attiny15l 1187h?avr?09/07 typical characteristics the following charts show typical behavior. these data are characterized but not tested. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l ?v cc ?f where c l = load capacitance, v cc = operating voltage and f = average switch- ing frequency of i/o pin. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the dif- ferential current drawn by the watchdog timer. figure 36. active supply current vs. v cc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.5 3 3.5 4 4.5 5 5.5 6 active supply current vs. v cc device clocked by 1.6mhz internal rc oscillator i cc (ma) v cc (v) t = 85 ? c a t = 25 ? c a 67 attiny15l 1187h?avr?09/07 figure 37. idle supply current vs. v cc figure 38. calibrated internal rc os cillator frequency vs. v cc 0 0.5 1 1.5 2 2.5 3 2.5 3 3.5 4 4.5 5 5.5 6 idle supply current vs. v cc device clocked by 1.6mhz internal rc oscillator i cc (ma) v cc (v) t = 85 ? c a t = 25 ? c a 0.88 0.90 0.92 0.94 0.96 0.98 1.00 1.02 2 2.5 3 3.5 4 4.5 5 5.5 6 25?c operating voltage (v) relative calibrated rc oscillator frequency vs. operating voltage t = 25 ? c a t = 85 ? c a t = 45 ? c a t = 70 ? c a frequency relative to nominal frequency at 25?c and v cc = 5.0v note: the nominal calibrated rc oscillator frequency is 1.6 mhz. 68 attiny15l 1187h?avr?09/07 figure 39. bandgap voltage vs. v cc figure 40. analog comparator offset voltage vs. common mode voltage note: 1. analog comparator offset voltage is measured as absolute offset. bandgap voltage vs. v cc measured with analog comparator v bg (v) v cc (v) 1.292 1.293 1.294 1.295 1.296 1.297 1.298 1.299 1.3 1.301 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a t = 45 ? c a t = 70 ? c a 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 analog comparator offset voltage vs. v = 5v cc common mode voltage common mode voltage (v) offset voltage (mv) t = 85 ? c a t = 25 ? c a 69 attiny15l 1187h?avr?09/07 figure 41. analog comparator offset voltage vs. common mode voltage figure 42. analog comparator input leakage current 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 analog comparator offset voltage vs. common mode voltage common mode voltage (v) offset voltage (mv) v = 2.7v cc t = 85 ? c a t = 25 ? c a 60 50 40 30 20 10 0 -10 0 0.5 1.5 1 2 2.5 3.5 3 4 4.5 5 6 6.5 7 5.5 analog comparator input leakage current t = 25 ? c a i (na) aclk v (v) in v = 6v cc 70 attiny15l 1187h?avr?09/07 figure 43. watchdog oscillator frequency vs. v cc note: 1. sink and source capabilities of i/o ports are measured on one pin at a time. figure 44. pull-up resistor current vs. input voltage 0 200 400 600 800 1000 1200 1400 1600 1,5 2 2,5 3 3,5 4 4,5 5 5,5 6 t = 85 ? c a t = 25 ? c a watchdog oscillator frequency vs. v cc v (v) cc f (khz) rc 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 pull-up resistor current vs. input voltage v = 5v cc i ( a) op v (v) op t = 85 ? c a t = 25 ? c a 71 attiny15l 1187h?avr?09/07 figure 45. pull-up resistor current vs. input voltage figure 46. i/o pin sink current vs. output voltage 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 pull-up resistor current vs. input voltage i ( a) op v (v) op v = 2.7v cc t = 85 ? c a t = 25 ? c a 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v = 5v cc i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a i/o pin sink current vs. output voltage 72 attiny15l 1187h?avr?09/07 figure 47. i/o pin source current vs. output voltage figure 48. i/o pin sink current vs. output voltage 0 2 4 6 8 10 12 14 16 18 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i/o pin source current vs. output voltage v = 5v cc i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a 0 5 10 15 20 25 0 0.5 1 1.5 2 i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a i/o pin sink current vs. output voltage v = 2.7v cc 73 attiny15l 1187h?avr?09/07 figure 49. i/o pin source current vs. output voltage figure 50. i/o pin input threshold voltage vs. v cc 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 i/o pin source current vs. output voltage i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a v = 2.7v cc 0 0.5 1 1.5 2 2.5 2.7 4.0 5.0 threshold voltage (v) v cc i/o pin input threshold voltage vs. v cc t = 25 ? c a 74 attiny15l 1187h?avr?09/07 figure 51. i/o pin input hysteresis vs. v cc 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 2.7 4.0 5.0 input hysteresis (v) v cc i/o pin input hysteresis vs. v cc t = 25 ? c a 75 attiny15l 1187h?avr?09/07 attiny15l register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f sreg i t h s v n z c page 11 $3e reserved $3c reserved $3b gimsk - int0 pcie - - - - - page 19 $3a gifr - intf0 pcif - - - - - page 20 $39 timsk -ocie1a - - - toie1 toie0 - page 20 $38 tifr -ocf1a - - - tov1 tov0 - page 21 $37 reserved $36 reserved $35 mcucr -pudsesm1sm0 - isc01 isc00 page 22 $34 mcusr - - - - wdrf borf extrf porf page 18 $33 tccr0 - - - - - cs02 cs01 cs00 page 27 $32 tcnt0 timer/counter0 (8-bit) page 28 $31 osccal oscillator calibration register page 24 $30 tccr1 ctc1 pwm1 com1a1 com1 a0 cs13 cs12 cs11 cs10 page 29 $2f tcnt1 timer/counter1 (8-bit) page 30 $2e ocr1a timer/counter1 output compare register a (8-bit) page 31 $2d ocr1b timer/counter1 output compare register b (8-bit) page 32 $2c sfior - - - - - foc1a psr1 psr0 page 26 $2b reserved $2a reserved $29 reserved $28 reserved $27 reserved $26 reserved $25 reserved $24 reserved $23 reserved $22 reserved $21 wdtcr - - - wdtoe wde wdp2 wdp1 wdp0 page 34 $20 reserved $1f reserved $1e eear - - eear5 eear4 eear3 eear2 eear1 eear0 page 36 $1d eedr eeprom data register (8-bit) page 36 $1c eecr - - - - eerie eemwe eewe eere page 37 $1b reserved $1a reserved $19 reserved $18 portb - - - portb4 portb3 portb2 portb1 portb0 page 51 $17 ddrb - - ddb5 ddb4 ddb3 ddb 2 ddb1 ddb0 page 51 $16 pinb - - pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 52 $15 reserved $14 reserved $13 reserved $12 reserved $11 reserved $10 reserved $0f reserved $0e reserved $0d reserved $0c reserved $0b reserved $0a reserved $09 reserved $08 acsr acd acbg aco aci acie - acis1 acis0 page 39 $07 admux refs1 refs0 adlar - - mux2 mux1 mux0 page 46 $06 adcsr aden adsc adfr adif adi e adps2 adps1 adps0 page 47 $05 adch adc data register high byte page 49 $04 adcl adc data register low byte page 49 ? reserved $00 reserved 76 attiny15l 1187h?avr?09/07 attiny15l instruction set summary mnemonic operands description operation flags # clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff - rd z,c,n,v 1 neg rd two?s complement rd $00 - rd z,c,n,v,h 1 sbr rd, k set bit(s) in register rd rd v k z,n,v 1 cbr rd, k clear bit(s) in register rd rd ? (ffh - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd - 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 rcall k relative subroutine call pc pc + k + 1 none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2 cp rd, rr compare rd - rr z,n,v,c,h 1 cpc rd, rr compare with carry rd - rr - c z,n,v,c,h 1 cpi rd, k compare register with immediate rd - k z,n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1/2 sbrs rr, b skip if bit in regist er is set if (rr(b) = 1) pc pc + 2 or 3 none 1/2 sbic p, b skip if bit in i/o register cleared if (p(b) = 0) pc pc + 2 or 3 none 1/2 sbis p, b skip if bit in i/o register is set if (p(b) = 1) pc pc + 2 or 3 none 1/2 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half-carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half-carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t-flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t-flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 data transfer instructions ld rd, z load register indirect rd (z) none 2 st z, rr store register indirect (z) rr none 2 mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd knone1 in rd, p in port rd pnone1 out p, rr out port p rr none 1 lpm load program memory r0 (z) none 3 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1none2 77 attiny15l 1187h?avr?09/07 cbi p, b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c, rd(n+1) rd(n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd(n) rd(n+1), c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4), rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half-carry flag in sreg h 1h1 clh clear half-carry flag in sreg h 0h1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 attiny15l instruction set summary (continued) mnemonic operands description operation flags # clocks 78 attiny15l 1187h?avr?09/07 note: 1. pb-free packaging, complies to the european directive for restriction of hazardous substances (rohs directive). also halide free and fully green. ordering information power supply speed (mhz) ordering code package operation range 2.7 - 5.5v 1.6 attiny15l-1pc attiny15l-1pu (1) attiny15l-1sc attiny15l-1su (1) 8p3 8p3 8s2 8s2 commercial (0 c to 70 c) attiny15l-1pi attiny15l-1pu (1) attiny15l-1si attiny15l-1su (1) 8p3 8p3 8s2 8s2 industrial (-40 c to 85 c) 79 attiny15l 1187h?avr?09/07 package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.200" wide, plastic gull wing small outline (eiaj soic) 80 attiny15l 1187h?avr?09/07 packaging information 8p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 81 attiny15l 1187h?avr?09/07 8s2 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 s 2 , 8 -le a d, 0.209" body, pl as tic s m a ll o u tline p a ck a ge (eiaj) 4/7/06 8s 2d common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to eiaj dr a wing edr-7 3 20 for a ddition a l inform a tion. 2. mi s m a tch of the u pper a nd lower die s a nd re s in bu rr s a re not incl u ded. 3 . it i s recommended th a t u pper a nd lower c a vitie s b e e qua l. if they a re different, the l a rger dimen s ion s h a ll b e reg a rded. 4. determine s the tr u e geometric po s ition. 5. v a l u e s b ,c a pply to pl a ted termin a l. the s t a nd a rd thickne ss of the pl a ting l a yer s h a ll me asu re b etween 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0. 3 5 0.4 8 5 c 0.15 0. 3 5 5 d 5.1 3 5. 3 5 e1 5.1 8 5.40 2, 3 e 7.70 8 .26 l 0.51 0. 8 5 0? 8 e 1.27 b s c 4 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d s ide view s i d e v i e w 82 attiny15l 1187h?avr?09/07 datasheet revision history rev h - 09/07 1. updated ?ordering information? on page 78. rev g - 06/07 1. ?not recommended for new design? . rev f - 06/05 1. updated v bot in table 4 on page 14 . 2. added ?unconnected pins? on page 51. 3. updated ?packaging information? on page 80. i attiny15l 1187h?avr?09/07 table of contents features............... ................. .............. .............. .............. .............. ......... 1 pin configuration....... ................. ................ ................. ................ ......... 1 description .......... ................. .............. .............. .............. .............. ......... 2 block diagram ...................................................................................................... 3 pin descriptions.................................................................................................... 4 internal oscillators ................................. .............................................................. 4 attiny15l architectural overview ............... ................ .............. ......... 5 the general purpose register file ...................................................................... 6 the alu ? arithmetic logic unit........................................................................... 6 the flash program memory ................................................................................. 6 the program and data addressing modes .......................................................... 7 subroutine and interrupt hardware stack ............................................................ 9 the eeprom data memory ................................................................................ 9 i/o memory ......................................................................................................... 10 reset and interrupt handling.............................................................................. 12 internal voltage reference ................................................................................. 18 interrupt handling ............................................................................................... 19 sleep modes....................................................................................................... 23 tuneable internal rc oscillator.......................................................................... 24 internal pll for fast peripheral clock generation ............................................. 24 timer/counters .......... ................. ................ ................. .............. ......... 25 the timer/counter0 prescaler ........................................................................... 25 the timer/counter1 prescaler ........................................................................... 25 the special function io register ? sfior........................................................ 26 the 8-bit timer/counter0.................................................................................... 26 the 8-bit timer/counter1.................................................................................... 28 the watchdog timer ........ .............. ............... .............. .............. ......... 34 eeprom read/write access..... ................ ................. .............. ......... 36 preventing eeprom corrupti on .................. ................ ................ ................. ..... 38 the analog comparator.......... ................. ................ ................. ......... 39 the analog-to-digital converter, anal og multiplexer, and gain stag- es................... ................. ................ ................. .............. .............. ......... 41 features.............................................................................................................. 41 operation ............................................................................................................ 42 prescaling and conversion timing ..................................................................... 43 adc noise canceler function............................................................................ 46 adc noise-canceling techniques ...................................................................... 50 adc characteristics ........................................................................................... 50 ii attiny15l 1187h?avr?09/07 i/o port b ............. .............. .............. ............... .............. .............. ......... 51 memory programming........... ................ ................. ................ ............ 54 program and data memory lock bits................................................................. 54 fuse bits............................................................................................................. 54 signature bytes .................................................................................................. 54 calibration byte .................................................................................................. 55 programming the flash ...................................................................................... 55 high-voltage serial programming....................................................................... 55 high-voltage serial programming algorithm....................................................... 56 high-voltage serial programming characteristics .............................................. 59 low-voltage serial downloading ........................................................................ 59 low-voltage serial programming characteristics............................................... 63 electrical characteristics...... ................ ................. ................ ............ 64 absolute maximum ratings ................................................................................ 64 dc characteristics.............................................................................................. 64 typical characteristics ......... ................ ................. ................ ............ 66 attiny15l register summary.... ................ ................. .............. ......... 75 attiny15l instruction set summa ry................ .............. ............ ....... 76 ordering information............. ................ ................. ................ ............ 78 packaging information .......... ................ ................. ................ ............ 79 8p3 ..................................................................................................................... 79 8s2 ..................................................................................................................... 80 datasheet revision hi story............. ............... .............. .............. ......... 81 rev h - 09/07...................................................................................................... 81 rev g - 06/07 ..................................................................................................... 81 rev f - 06/05 ...................................................................................................... 81 table of contents ................ .............. .............. .............. .............. .......... i 1187h?avr?09/07 ? atmel corporation 2005 . all rights reserved. atmel ? , logo and combinations thereof, avr ? and others are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. |
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